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experience

Technical Intern

FPGA prototyping, Synopsys

Duration: 6 Jan 2019 - 5 June 2019

Ethernet IP validation using FPGAs.

Under supervision of Manjunath M B,

a. Worked on FPGA prototyping using HAPS (High-performance ASIC Prototyping Systems).

b. Was responsible for XLGMAC Ethernet inter-op generation and validation for 25GHz PHY.

c. Ramped up on the Ethernet protocol, Ethernet MAC, and PCS controllers.

d. Demonstrated PRBS (Pseudo-Random Binary Sequence) generation, reception for interconnect validation.

Design Engineer II

Physical design of SerDes IPs, Cadence Design Systems

Duration: 7 June 2019 - 30 July 2019

Netlist-GDSII physical design of SerDes IPs in cutting edge technology nodes like 5, 7 & 16 nm.

Under supervision of Vikas Jayathilakan,

a. Implemented PCIe Gen 3, 4 - SerDes and D-PHY IP designs in 5, 7 and 16 nm technology nodes.

b. Was responsible for the complete back-end digital design flow – netlist to GDSII.

c. Took ownership of design blocks with power-domains, wherein major work involved clock skew analysis, in-rush analysis, timing analysis (up to 2.5GHz clock frequencies) and physical verification.

d. Underwent training on Test Chip implementation – from Bump Floor-planning to RDL routing.

e. Demonstrated proficiency in automation and text-parsing.

f. Apart from projects, took initiative and developed a generic leakage and setup optimization flow.

Graduate Research Assistant

Prof. Sung-Kyu Lim's (GTCAD) lab, Georgia Institute of Technology

Duration: 25 August 2021 - Present

I worked on enabling novel physical design methodologies ranging from Back-side Clock Delivery Network, Hierarchical 3D designs & Automatic Floorplan generation and validation, and Macro-Partitioning & Thermal modeling

Under supervision of Prof. Sung-Kyu Lim, I worked on the following projects,

1) Back-side Clock Delivery Network Physical Design methodology:

a. First-ever EDA methodology that utilizes the back-side metals for clock routing.

b. Intelligently partitioned a given clock tree to utilize the back vs. front-side to improve clock and full-chip metrics while minimizing through-silicon-via usage.

c. Results on commercial core processors show that Back-side Clock Delivery Network methodology leads to 14% performance, 5% power, and 70% signal integrity improvements.

d. Work was done in collaboration with IMEC.

2) Hierarchical 3D designs & Automatic Floorplan generation and validation:

a. Validated automatic floorplan and area-recovery capabilities in journal extension of Agnesina A., et. al., “Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face Bonded 3D ICs”, ACM/IEEE ISLPED, 2022.

b. Worked on physical implementation methodologies of 3D (Memory-on-Logic) & (Logic-on-Logic) Stacking Architectures.

c. Successfully implemented designs with instance counts up to 9M, using commercial 2D and in-house 3D Place and Route tools at advanced technology nodes.

d. Evaluated 3D Automatic Floorplanning solutions with respect to the existing 3D Manual Floorplanning solutions.

3) Macro partitioning & Thermal modeling:

a. Lingjun Zhu, Nesara Bethur, et. al., “3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs”, ACM/IEEE ISLPED, 2022.

b. Contributed to developing a thermal analysis flow for 2D and 3D Designs including an ARM core.

c. Generated Chip Thermal Models (CTM) using Ansys Redhawk and analyzed thermal resistances (Rja, Rjb and Rjc), temperature trends and heat flow changes by varying interconnect density, cooling solution, bonding material, heatsink and board size using Ansys CPS.

d. Developed automation scripts to create fins and pins on heatsinks in CPS and analyzed their impacts on temperature.

e. Explored various heatsink designs and water-cooling modelling, saw max temperature drop from ~200C to ~60C.

portfolio

Portfolio item number 1

Short description of portfolio item number 1

Portfolio item number 2

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projects

Classifying toxic memes with AI

Built a DNN for the multi-modal classification of toxic memes and explored early and late fusion techniques. (Link to project site)

ISWAP - Interposer SWAP

A deadlock removal scheme adaptable to heterogenous 2.5D interconnect networks which was implemented in gem5 garnet simulator.

Out-of-Order Pipeline with In-order Commit

Implemented a timing simulation of Out-of-Order Pipeline with in-order commit using Reorder Buffer and Register Alias Table in C++.

Utility-Based Cache Partitioning Implementation

Implemented Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches in C++.

Self-tuning DVS processor implementation

Implemented A self-tuning DVS processor using delay-error detection and correction in Cadence Virtuoso.

Leakage and Setup Optimization Flow

Developed a flow that involved path-based VT-swapping, which was used across different projects that effectively recovered around 15% of leakage power and 60% of TNS (Total Negative Slack) of setup and hold.

publications

3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs

Published in ISLPED, 2022

In this paper, we evaluate and quantify the impacts of various macro partitioning on the performance and temperature in commercial-grade 3D ICs. In addition, we propose a set of partitioning guidelines and a quick constraint-graph-based approach to create floorplans for logic-on-memory 3D ICs.

Recommended citation: Lingjun Zhu, Nesara Bethur, et. al., "3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs", ACM/IEEE ISLPED, 2022. [PDF](https://dl.acm.org/doi/abs/10.1145/3531437.3539724)

teaching

Teaching experience 1

Undergraduate course, University 1, Department, 2014

This is a description of a teaching experience. You can use markdown like any other post.

Teaching experience 2

Workshop, University 1, Department, 2015