3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs
Published in ISLPED, 2022
In this paper, we evaluate and quantify the impacts of various macro partitioning on the performance and temperature in commercial-grade 3D ICs. In addition, we propose a set of partitioning guidelines and a quick constraint-graph-based approach to create floorplans for logic-on-memory 3D ICs.
Recommended citation: Lingjun Zhu, Nesara Bethur, et. al., "3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs", ACM/IEEE ISLPED, 2022. [PDF](https://dl.acm.org/doi/abs/10.1145/3531437.3539724)